目次

Keynote Papers: Half a Century of Logic Synthesis (E.J. McCluskey). IsHigh Level Synthesis Practical? (R. Composano). High Level Synthesis.Symbolic Don't Cares and Equivalence in High-Level Synthesis (B. Lin,G.S. Whitcomb, A.R. Newton). Scheduling of Large Signal Flow GraphsBased on Metric Graph Clustering (F. Depuydt et al.). Profit-Loss-GainAlgorithm for Data-Path Synthesis (V. Techangam, A. Pitaksanonkul, C.Lursinap). A Novel Scheduling/Allocation Approach for DatapathSynthesis Based on Genetic Paradigms (N. Wehn, M. Held, M. Glesner).Port Assignment in Multiport Memories for Interconnection Minimizationin Datapath Synthesis (T.C. Wilson et al.). Automatic Generation ofSingle Chip Multi Processor Systems (H.J. Kramer, W. Rosenstiel). AHigh-Level Synthesis Tool for Exploiting Pipelines in Special-PurposeSystems (B. Fjellborg). A High-Level Synthesis Algorithm Based on AreaOriented Design Transformations (W. Schenk). Logic and ArchitectureSynthesis. OASIS: A Silicon Compiler for Semi-Custom Design (G. Kedem,F. Brglez, K. Kozminski). High-Level Synthesis and OptimizationStrategies in Hercules and Hebe (D. Ku, G. De Micheli). CASTOR: StateAssignment in a Finite State Machine Synthesis System (G. Rietsche, M.Neher). Multi-Level Synthesis on Programmable Devices in the AsylSystem (G. Saucier, P. Sicard, L. Bouchet). A Methodology forPerformance Driven Data-Path Compilation (S. Note et al.). AutomaticSynthesis of mu Programmed Controllers (L. Gerbaux, G. Saucier).Controller Synthesis. The Structure of Constant Rank State Machines(N.F. Benschop). State Reduction of Incompletely Specified FiniteSequential Machines (M.J. Avedillo, J.M. Quintana, J.L. Huertas).Determining the Optimal Cycle Time in Controller Synthesis (R. Zahir,W. Fichtner). A Formal Approach to Control-Unit Synthesis (M. Mahmood,F. Mavaddat, M.I. Elmasry). Low Level Synthesis. Efficient Computationof Exact and Simplified Observability Don't Care Sets forMultiple-Level Combinatorial Networks (M. Damiani, G. De Micheli).Lexicographical Factorization Minimizing the Critical Path and theRouting Factor of Multilevel Logic (P. Abouzeid, G. Saucier, F.Poirot). Corolla Partitions and Don't Cares (S. Dey, F. Brglez, G.Kedem). Combining Serial Decomposition with Topological Partitioningfor Effective Multi-Level PLA Implementations (T. Luba et al.).Redesign and Automatic Error Correction of Combinatorial Circuits (M.Fujita, T. Kakuda, Y. Matsunaga). Technology Mapping. Automatic Layoutof CMOS Cells (R. Jamier, J. Frehel). BAGDAD: An Oriented Layout CellSynthesizer (J. Cloutier, J. Zahnd). Flexible and Optimizing ALUSynthesis (F. Buijs, P. Vogelgesang, T. Lengauer). Building BlockGeneration Considering the Inherent Hierarchy of Arithmetic Operations(A. Munzner). A Fast and Effective Technology Mapper on an AutodualLibrary of Standard Cells (K. Sakouti, G. Saucier). Case Studies.