目次

RTL TO GDSII, OR SYNTHESIS, PLACE, AND ROUTE Design FlowsDavid Chinnery, Leon Stok, David Hathaway, and Kurt Keutzer Logic SynthesisSunil P. Khatri and Narendra V. Shenoy Power Analysis and Optimization from Circuit to Register-Transfer LevelsJosé Monteiro, Rakesh Patel, and Vivek Tiwari Equivalence CheckingAndreas Kuehlmann and Fabio Somenzi Digital Layout: PlacementAndrew B. Kahng and Sherief Reda Static Timing AnalysisJordi Cortadella and Sachin S. Sapatnekar Structured Digital DesignMinsik Cho, Mihir Choudhury, Ruchir Puri, Haoxing Ren, Hua Xiang, Gi-Joon Nam, Fan Mo, and Robert K. Brayton RoutingGustavo E. Téllez, Jin Hu, and Yaoguang Wei Physical Design for 3D ICsSung-Kyu Lim Gate SizingStephan Held and Jiang Hu Clock Design and SynthesisMatthew R. Guthaus Exploring Challenges of Libraries for Electronic DesignJames Hogan, Scott T. Becker, and Neal Carney Design ClosurePeter J. Osler, John M. Cohn, and David Chinnery Tools for Chip-Package CodesignPaul D. Franzon and Madhavan Swaminathan Design DatabasesMark Bales FPGA Synthesis and Physical DesignMike Hutton, Vaughn Betz, and Jason Anderson ANALOG AND MIXED-SIGNAL DESIGN Simulation of Analog and RF Circuits and SystemsJaijeet Roychowdhury and Alan Mantooth Simulation and Modeling for Analog and Mixed-Signal Integrated CircuitsGeorges G.E. Gielen and Joel R. Phillips Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A SurveyRob A. Rutenbar, John M. Cohn, Mark Po-Hung Lin, and Faik Baskaya PHYSICAL VERIFICATION Design Rule CheckingRobert Todd, Laurence Grodd, Jimmy Tomblin, Katherine Fetty, and Daniel Liddell Resolution Enhancement Techniques and Mask Data PreparationFranklin M. Schellenberg Design for Manufacturability in the Nanometer EraNicola Dragone, Carlo Guardiani, and Andrzej J. Strojwas Design and Analysis of Power Supply NetworksRajendran Panda, Sanjay Pant, David Blaauw, and Rajat Chaudhry Noise in Digital ICsIgor Keller and Vinod Kariat Layout ExtractionWilliam Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh, Peter Spink, and Louis K. Scheffer Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and ValidationNishath Verghese and Makoto Nagata TECHNOLOGY CAD Process SimulationMark D. Johnson Device Modeling: From Physics to Electrical Parameter ExtractionRobert W. Dutton, Chang-Hoon Choi, and Edwin C. Kan High-Accuracy Parasitic ExtractionMattan Kamon and Ralph Iverson